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PIC16(L)F722A/723A

DS41417B-page 106

2010-2012 Microchip Technology Inc.

12.6

Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Count

Enable.

Timer1 gate can also be driven by multiple selectable

sources.

12.6.1

TIMER1 GATE COUNT ENABLE

The Timer1 gate is enabled by setting the TMR1GE bit

of the T1GCON register. The polarity of the Timer1 gate

is configured using the T1GPOL bit of the T1GCON

When Timer1 Gate (T1G) input is active, Timer1 will

increment on the rising edge of the Timer1 clock

source. When Timer1 gate input is inactive, no

incrementing will occur and Timer1 will hold the current

count. See Figure 12-3 for timing details.

12.6.2

TIMER1 GATE SOURCE

SELECTION

The Timer1 gate source can be selected from one of

four different sources. Source selection is controlled by

the T1GSS bits of the T1GCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the T1GPOL bit of the

T1GCON register.

TABLE 12-4:

TIMER1 GATE SOURCES

12.6.2.1

T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

12.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-

high pulse will automatically be generated and inter-

nally supplied to the Timer1 gate circuitry.

12.6.2.3

Timer2 Match Gate Operation

The TMR2 register will increment until it matches the

value in the PR2 register. On the very next increment

cycle, TMR2 will be reset to 00h. When this Reset

occurs, a low-to-high pulse will automatically be

generated and internally supplied to the Timer1 gate

circuitry.

12.6.2.4

Watchdog Overflow Gate Operation

The Watchdog Timer oscillator, prescaler and counter

will be automatically turned on when TMR1GE = 1 and

T1GSS selects the WDT as a gate source for Timer1

(T1GSS = 11). TMR1ON does not factor into the oscil-

lator, prescaler and counter enable. See Table 12-5.

The PSA and PS bits of the OPTION register still

control what time-out interval is selected. Changing the

prescaler during operation may result in a spurious

capture.

Enabling the Watchdog Timer oscillator does not

automatically enable a Watchdog Reset or Wake-up

from Sleep upon counter overflow.

As the gate signal coming from the WDT counter will

generate different pulse widths depending on if the

WDT is enabled, when the CLRWDT instruction is

executed, and so on, Toggle mode must be used. A

specific sequence is required to put the device into the

correct state to capture the next WDT counter interval.

TABLE 12-3:

TIMER1 GATE ENABLE

SELECTIONS

T1CLK

T1GPOL

T1G

Timer1 Operation

Counts

Holds Count

Counts

T1GSS

Timer1 Gate Source

Timer1 Gate Pin

Overflow of Timer0

(TMR0 increments from FFh to 00h)

Timer2 match PR2

(TMR2 increments to match PR2)

Count Enabled by WDT Overflow

(Watchdog Time-out interval expired)

Note:

When using the WDT as a gate source for

Timer1, operations that clear the Watchdog

Timer (CLRWDT, SLEEP instructions) will

affect the time interval being measured for

capacitive sensing. This includes waking

from Sleep. All other interrupts that might

wake the device from Sleep should be

disabled to prevent them from disturbing

the measurement period.

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